Officers of Year 2008

Chair Person: Tsutomu Sasao Kyushu Institute of Technology
Vice Chair Person: Vasily Moshnyaga Fukuoka University
Secretary/Treasurer: Toshinori Sato Fukuoka University

2008 Activity Reports

December 1, Technical Meeting

Title Joint Seminar on Advanced LSI Test Technology
Presenters Prof. M. Tehranipoor (University of Connecticut, USA)
Prof. K. Miyase (Kyushu Institute of Technology, Japan)
Prof. M. Yoshimura (Kyushu University, Japan)

Prof. Tehranipoor
Place Fukuoka Institute of System LSI Design Industry, 2F Meeting Room A
3-8-33, Momochihama, Sawara-ku, Fukuoka
(Advanced registration required. See below)
DATE December 1, 2008 (Mon.) 13:30 - 16:50
Attendees 29 (including 7 IEEE members)
Abstract Part I: Power-Aware Testing of Deep Submicron Designs
1. Dealing with Power and Signal Integrity Issues during Test of Very Deep Submicron Designs
   Prof. M. Tehranipoor (University of Connecticut, USA)
2. Methodology and System for Deducing Power Supply Noise in At-Speed Scan Testing
   Prof. K. Miyase (Kyushu Institute of Technology, Japan)
Part II: Security-Assuring of Integrated Circuits
1. Verifying Trustworthiness of Integrated Circuits
   Prof. M. Tehranipoor (University of Connecticut, USA)
2. Design For Testability Methods against Scan based Attacks
   Prof. M. Yoshimura (Kyushu University, Japan)
Registration Ms. Maiko Mori

October 19-21, Technical Meeting

Title IPSJ SIGARC Meeting

Prof. Yasuura                                                   Prof. Miyoshi

Prof. Kise                                                   Entrance

Place Daikanso
1-21-1, Yumachi, Chikushino, Fukuoka
DATE October 19 (Sun.) - 21 (Tue.), 2008
Attendees 45 (including 16 IEEE members)
Abstract Please refer IPSJ's event information.

October 19, 2008
- Panel on how to attend leading international conferences
October 20, 2008
- Oral sessions
- Invited speech: Social System Architecture on Information Technology
   Professor Hiroto Yasuura (Kyushu University)
- Panel on requests from industories to university research in Japan
October 21, 2008
- Oral sessions

August 8, Technical Meeting

Title Network-on-Chip Architecture (slide)
Presenter Dr. Hiroki Matsutani (Keio University)

Dr. Matsutani
Place Fukuoka Institute of System LSI Design Industry, 2F Meeting Room A
3-8-33, Momochihama, Sawara-ku, Fukuoka
DATE August 8, 2008 (Fri.) 14:00 - 15:30
Attendees 16 (including 6 IEEE members)
Abstract Abstract: The advances made in semiconductor technology have allowed us to integrate a number of processing cores on a single chip. To connect such many cores, Network-on-Chips (NoCs) that introduce a packet-switched network structure have been widely employed instead of traditional bus-based on-chip interconnects. In this talk, deadlock-free packet routing schemes and network topologies used in recent NoCs are first introduced. On-chip router architecture is illustrated based on a simple wormhole router design. Then, evaluation methodology and tools for NoCs are briefly introduced. Finally some of recent research topics on NoCs are surveyed, and the prediction router, which predictively skips one or more router pipeline stages to reduce the communication latency, is introduced as one of our recent activities.

Presenter biography: Dr. Hiroki Matsutani received the Ph.D degree in engineering in 2008. He is now a visiting researcher at Graduate school of science and technology, Keio University, Japan. He is also a JSPS research fellowships for young scientists.

July 16, Technical Meeting

Title 1. An Optimization Framework for Embedded Processors with Auto-Addressing Mode
2. Challenges and Approaches in Providing Quality of Service in Chip Multi-Processor Systems
Presenters 1. Prof. Santosh Pande (Georgia Institute of Technology)
2. Prof. Yan Solihin (North Carolina State University)

Prof. Solihin
Place Fukuoka Institute of System LSI Design Industry, 2F Meeting Room A
3-8-33, Momochihama, Sawara-ku, Fukuoka
DATE July 16, 2008 (Thu.) 10:00 - 12:00
Attendees 12 (including 6 IEEE members)
Abstract 1. An Optimization Framework for Embedded Processors with Auto-Addressing Mode
Modern embedded processors with dedicated address generation unit support memory accesses through auto-increment/decrement addressing mode. The auto-increment/decrement mode, if properly utilized, can save address arithmetic instructions, reduce static and dynamic memory footprint of the program and speed up the execution as well.
[Liao 1995; 1996] categorized this problem as simple offset assignment (SOA) and general offset assignment (GOA), which involves storage layout of variables and assignment of address registers respectively proposing several heuristic solutions. Two important directions of work have been followed subsequently for solving the SOA problem: the first one involves coming up with better heuristics for graph algorithms for offset assignment and second one involves improving the performance of Liao's solution by undertaking program reordering which rearranges the code sequence.
This work proposes a *new direction* for investigating the solution space of the problem. The general idea is to perform simplification of the underlying access graph through coalescence of the memory locations of program variables. A comprehensive framework is proposed including coalescence-based offset assignment and post-pre optimization. Variables not interfering with other (not simultaneously live at any program point) can be coalesced into the same memory location. Coalescing allows simplifications of the access graph yielding better SOA solutions; it also reduces the address register pressure to such low values that some GOA solutions become optimal. Moreover, it can reduce the memory footprint both statically and at runtime for stack variables. Besides, variable coalescence is orthogonal to other heuristics earlier proposed and thus can be integrated with the other approaches. A key limitation to the use of auto-addressing modes by production compilers is the limited scope of its applicability. Typically, this optimization has been performed only within basic blocks which severely limits its utility. Our second optimization (post/pre optimization) considers both post- and pre- modification mode for optimizing code across basic blocks which makes it useful. Making use of both addressing modes further reduces SOA/GOA cost and our post-pre optimization phase is optimal in selecting post or pre mode after variable offsets have been determined.
We have shown the advantages of our framework over previous approaches to capture more opportunities to reduce both stack size and SOA/GOA cost leading to more speedup. The algorithms are evaluated on a commercial compiler provided by Motorola to boost code generation performance on the DSP 56000 chip. Our results show that the cost can be reduced by 70~80% for Single-AR and Multiple-AR, almost doubling the cost reduction from a baseline solver. On the other hand, coalescence-based approach can also shrink the stack size a lot. We observe a significant reduction of 63~74% for Single-AR and Multiple-AR. Furthermore, the optimization phases after coalescence-based offset assignment including program reordering and post/pre optimization contribute to more cost reduction as well. The overall cycle reduction is up to 8.28%.

2. Challenges and Approaches in Providing Quality of Service in Chip Multi-Processor Systems
In this talk, I will discuss problems related to the impact of sharing fine-grain platform resources among cores, for example the lowest level cache. We will show how different applications are affected by cache sharing. In particular, we will highlight the types and severity of pathological performance cases that can arise when applications run together on different cores but sharing the lowest level cache.
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse in terms of performance, reliability, and availability requirements. In this environment, it is desirable to have microarchitecture and software support that can provide a guarantee of a certain level of performance (Quality of Service or QoS). We will present a framework for multicore architectures to fully provide QoS. We found that in addition to the ability to partition platform resources, a full QoS framework also needs an appropriate way to specify a QoS target, and an admission control policy that accepts jobs only when their QoS targets can be satisfied. We also found that providing strict QoS often leads to a significant reduction in throughput due to resource fragmentation. We will show throughput optimization techniques that include: (1) exploiting various QoS execution modes, and (2) a microarchitecture technique that steals excess resources from a job while still meeting its QoS target.

July 10, IEEE CAS Fukuoka Chapter Technical Meeting

Title Inter-Chip Communications for 3D System Integration
- Opportunities in More than Moore - (slide)
Presenter Professor Tadahiro Kuroda (Electrical Engineering, Keio University)
Place Fukuoka Institute of System LSI Design Industry, 2F Meeting Room B
3-8-33, Momochihama, Sawara-ku, Fukuoka
DATE July 10, 2008 (Thu.) 15:00 - 16:30
Attendees 29 (including 11 IEEE members)
Abstract Abstract: Scaling of CMOS integrated circuits is becoming difficult due to increase in power dissipation and device variations. Two future directions in IC technology are in prospect; "More Moore" by the conventional device scaling and "More than Moore" by System-in-Package (SiP). This talk will present some of the recent research achievements on 3D system integration by SiP. Especially focus will be placed on CMOS proximity inter-chip communications. Capacitive and inductive coupling I/Os are emerging non-contact parallel links for chips that are stacked in a package. They are implemented by digital circuits in a standard CMOS. No new wafer process or mechanical process is required, and hence inexpensive. Since there is no pad exposed for contact, ESD protection structure can be removed. Chips under difference supply voltages can be directly connected, because they provide with an AC-coupling interface. In the talk, fundamental differences between the inductive coupling and the capacitive coupling will be discussed. Advantages of the inductive coupling over Through-Silicon-Vias and micro-bumps will then be referred to. Circuit techniques to raise aggregated data rate to 1Tb/s, perform burst data transmission at 11Gb/s/channel, lower energy dissipation to 0.1pJ/b, and extend communication ranges over 1mm will be presented. Lastly, future challenges and opportunities such as a 3D scaling scenario will be described.

Presenter biography: Tadahiro Kuroda received the Ph.D. degree in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1999. In 1982, he joined Toshiba Corporation, where he designed CMOS SRAMs, gate arrays and standard cells. From 1988 to 1990, he was a Visiting Scholar with the University of California, Berkeley, where he conducted research in the field of VLSI CAD. In 1990, he was back to Toshiba, and engaged in the research and development of BiCMOS ASICs, ECL gate arrays, high-speed CMOS LSIs for telecommunications, and low-power CMOS LSIs for multimedia and mobile applications. He invented a Variable Threshold-voltage CMOS (VTCMOS) technology to control VTH through substrate bias, and applied it to a DCT core processor and a gate-array in 1995. He also developed a Variable Supply-voltage scheme using an embedded DC-DC converter, and employed it to a microprocessor core and an MPEG-4 chip for the first time in the world in 1997. In 2000, he moved to Keio University, Yokohama, Japan, where he has been a professor since 2002. He was a Visiting Professor at Hiroshima University, Japan, and is a Visiting MacKay Professor at the University of California, Berkeley. His research interests include ubiquitous electronics, sensor networks, wireless and wireline communications, and ultra-low-power CMOS circuits. He has published more than 200 technical publications, including 50 invited papers, and 18 books/chapters, and has filed more than 100 patents. Dr. Kuroda served as the General Chairman for the Symposium on VLSI Circuits, the Vice Chairman for ASP-DAC, sub-committee chairs for A-SSCC, ICCAD, and SSDM, and program committee members for the Symposium on VLSI Circuits, CICC, DAC, ASP-DAC, ISLPED, SSDM, ISQED, and other international conferences. He is a recipient of the 2005 IEEE System LSI Award, the 2005 P&I Patent of the Year Award, the 2006 LSI IP Design Award, the 2006 IP/SoC Best Design Paper Award, and the 2007 ASP-DAC Best Design Award. He is an IEEE Fellow, an elected AdCom member for the IEEE Solid-State Circuits Society and an IEEE SSCS Distinguished Lecturer.

March 31, IEEE CAS Society President, Prof. Ogorzalek u

Title Statistical learning techniques for bio-medical applications
Presenter Maciej Ogorzalek (Jagiellonian Univ., Poland)
Place Kyushu University, Ito Campus, West No. 2, 3F 325
DATE March 31, 2008 (Mon.) 14:30 - 17:00
Abstract 14:30-16:00 wRecent Advances in Research on Circuits and Systems at Kyushu Universityx (*speaker)
(1) "New AD/DA Conversion Using Chaotic Dynamics" Satoshi Hironaka and *Tohru Kohda (Kyushu Univ.) and Kazuyuki Aihara (ERATO, JST, Tokyo Univ.)
(2) "How to Make Use of Gaussian Pulse Function in Communication Systems" *Yutaka Jitsumatsu and Tohru Kohda (Kyushu Univ.)
(3) "Analysis and Synthesis of Piecewise-Linear Recurrent Neural Networks Generating Periodic Sequences of Binary Patterns" *Norikazu Takahashi and Yasuhiro Minetoma (Kyushu Univ.)
16:00-17:00 wCASS President, Prof. Ogorzalek ux
In many bio-medical measurements bring us very large data sets representing various observables and signals such as eg. ECG, EEG, images of organs, recordings of voice etc. Measured data requires further interpretation and processing. Statistical learning techniques provide very powerful tools for data and signal modeling and classification. This lecture discusses a special type of techniques allowing for building of ensembeles of models. It can be shown that a carefuly chosen ensemble of diverse models can outperform any of the individual models in the set. We consider models which range from linear regression, neural networks, perceptrons, RBF networks, SVM and others. Special toolkit has been built in Matlab and C++ to implement these methods and build ensembles. The toolkit has been applied in modeling of ECGs, classification of viral data, searching solutions in drug design problems.

Jan. 19, Waseda Global COE International Symposium on Ambient SoC

Title: Waseda Global COE International Symposium on Ambient SoC
"Toward Ambient Information Society"
Detail Check the Program
Place Conference Center in Hibikino (2-3 Hibikino, Wakamatsu, Kitakyushu)
Date & Time Jan. 19, 2008 (Sat.) 9:30 - 17:10